VLSI-SoC: Research Trends in VLSI and Systems on Chip: Fourteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC2006), October 16-18, 2006, Nice, France

Author:   Giovanni De Micheli ,  Salvador Mir ,  Ricardo Reis
Publisher:   Springer-Verlag New York Inc.
Edition:   2008 ed.
Volume:   249
ISBN:  

9780387749082


Pages:   394
Publication Date:   15 November 2007
Format:   Hardback
Availability:   Awaiting stock   Availability explained
The supplier is currently out of stock of this item. It will be ordered for you and placed on backorder. Once it does come back in stock, we will ship it out for you.

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VLSI-SoC: Research Trends in VLSI and Systems on Chip: Fourteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC2006), October 16-18, 2006, Nice, France


Overview

This book contains extended and revised versions of the best papers that were presented during the fourteenth edition of the IFIP TC10/WG10.5 International Conference on Very Large Scale Integration, a global System-on-a-Chip Design & CAD conference. The 14th conference was held at the Hotel Boscolo, Nice, France (October 16-18, 2006). Previous conferences have taken place in Edinburgh, Trondheim, Vancouver, Munich, Grenoble, Tokyo, Gramado, Lisbon, Montpellier, Darmstadt and Perth. The purpose of this conference, sponsored by IFIP TC 10 Working Group 10.5 and by the IEEE Council on Electronic Design Automation (CEDA), is to provide a forum to exchange ideas and show industrial and academic research results in the field of microelectronics design. The current trend toward increasing chip integration and technology process advancements brings about stimulating new challenges both at the physical and system-design levels, as well in the test of these systems. VLSI- SOC conferences aim to address these exciting new issues.

Full Product Details

Author:   Giovanni De Micheli ,  Salvador Mir ,  Ricardo Reis
Publisher:   Springer-Verlag New York Inc.
Imprint:   Springer-Verlag New York Inc.
Edition:   2008 ed.
Volume:   249
Dimensions:   Width: 15.50cm , Height: 2.30cm , Length: 23.50cm
Weight:   0.769kg
ISBN:  

9780387749082


ISBN 10:   038774908
Pages:   394
Publication Date:   15 November 2007
Audience:   College/higher education ,  Professional and scholarly ,  Postgraduate, Research & Scholarly ,  Professional & Vocational
Format:   Hardback
Publisher's Status:   Active
Availability:   Awaiting stock   Availability explained
The supplier is currently out of stock of this item. It will be ordered for you and placed on backorder. Once it does come back in stock, we will ship it out for you.

Table of Contents

Architectures for High Dynamic Range, High Speed Image Sensor Readout Circuits.- Oversampled Time Estimation Techniques for Precision Photonic Detectors.- Innovative Optoeletronic Approaches to Biomolecular Analysis with Arrays of Silicon Devices.- Electronic Detection of DNA Adsorption and Hybridization.- Probabilistic amp; Statistical Design—the Wave of the Future.- A CMOS Mixed-Mode Sample-and-Hold Circuit for Pipelined ADCs.- Probabilistic Design: A Survey of Probabilistic CMOS Technology and Future Directions for Terascale IC Design.- Reliability Issues in Deep Deep Submicron Technologies: Time-Dependent Variability and its Impact on Embedded System Design.- Soft Error Resilient System Design through Error Correction.- Library Compatible Variational Delay Computation.- A Power-Efficient Methodology for Mapping Applications on Multi-Processor, System-on-Chip Architectures.- Frequency and Speed Setting for Energy Conservation in Autonomous Mobile Robots.- Configurable On-Line Global Energy Optimization in Multi-Core Embedded Systems Using Principles of Analog Computation.- Logic Synthesis of EXOR Projected Sum of Products.- A Method for I/O Pins Partitioning Targeting 3D VLSI Circuits.- CAT Platform for Analogue and Mixed-Signal Test Evaluation and Optimization.- Broadside Transition Test Generation for Partial Scan Circuits through Stuck-at Test Generation.- Comparison of an Æthereal Network on Chip and Traditional Interconnects - Two Case Studies.- Designing Routing and Message-Dependent Deadlock Free Networks on Chips.- Dynamic Reconfigurable Architecture Exploration based on Parameterized Reconfigurable Processor Model.- Human++: Emerging Technology for Body Area Networks.

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