Overview

Integrated circuit densities and operating speeds continue to rise at an exponential rate. Chips, however, cannot get larger and faster without a sharp decrease in power consumption beyond the current levels. Minimization of power consumption in VLSI chips has thus become an important design objective. In fact, with the explosive growth in demand for portable electronics and the usual push toward more complex functionality and higher performance, power consumption has in many cases become the limiting factor in satisfying the market demand. A new generation of power-conscious CAD tools are coming onto the market to help designers estimate, optimize and verify power consumption levels at most stages of the IC design process. These tools are especially prevalent at the register-transfer level and below. There is a great need for similar tools and capabilities at the behavioural and system levels of the design process. Many researchers and CAD tool developers are working on high-level power modelling and estimation, as well as power-constrained high-level synthesis and optimization. Techniques and tools alone are, however, insufficient to optimize VLSI circuit power dissipation, a consistent and convergent design methodology is also required. This book was written to address some of the key problems in power analysis and optimization early in the design process. In particular, it focuses on power macro-modelling based on regression analysis and power minimization through behavioural transformations, scheduling, resource assignment and hardware/software partitioning and mapping. What differentiates this book from other published work on the subject is the mathematical basis and formalism behind the algorithms and the optimality of these algorithms subject to the stated assumptions.

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