Overview

The quest for higher performance digital systems for applications such as gen­ eral purpose computing, signal/image processing, and telecommunications and an increasing cost consciousness have led to a major thrust for high speed VLSI systems implemented in inexpensive and widely available technologies such as CMOS. This monograph, based on the first author's doctoral dissertation, con­ centrates on the technique of wave pipelining as one method toward achieving this goal. The primary focus of this monograph is to provide a coherent pre­ sentation of the theory of wave pipelined operation of digital circuits and to discuss practical design techniques for the realization of wave pipelined circuits in the CMOS technology. Wave pipelining can be applied to a variety of cir­ cuits for increased performance. For example, many architectures that support systolic computation lend themselves to wave pipelined realization. Also, the wave pipeline design methodology emphasizes the role of controlled clock skew in extracting enhanced performance from circuits that are not deeply pipelined. Wave pipelining (also known as maximal rate pipelining) is a timing method­ ology used in digital systems to increase the number of effective pipeline stages without increasing the number of physical registers in the pipeline. Using this technique, new data is applied to the inputs of a combinational logic block be­ fore the outputs due to previous inputs are available thus effectively pipelining the combinational logic and maximizing the utilization of the logic.

Full Product Details

Author:   C. Thomas Gray ,  Wentai Liu ,  Ralph K. Cavin, III
Publisher:   Springer-Verlag New York Inc.
Imprint:   Springer-Verlag New York Inc.
Edition:   Softcover reprint of the original 1st ed. 1994
Volume:   248
Dimensions:   Width: 15.50cm , Height: 1.20cm , Length: 23.50cm
Weight:   0.355kg
ISBN:  

9781461364078

ISBN 10:   1461364078
Pages:   206
Publication Date:   27 September 2012
Audience:   Professional and scholarly ,  Professional & Vocational
Format:   Paperback
Publisher's Status:   Active
Availability:   Manufactured on demand  
We will order this item for you from a manufactured on demand supplier.

Table of Contents

1 Introduction and Motivation.- 1.1 Wave Pipelining.- 1.2 History.- 1.3 Designing Wave Pipelined Circuits.- 1.4 Organization.- 2 Clock Period Constraints: Single Stage Systems.- 2.1 Introduction.- 2.2 System Model.- 2.3 Constraints for Correct Clocking.- 2.4 Minimizing the Clock Period.- 2.5 The Parameter k.- 2.6 Special Cases.- 2.7 Conclusions.- 3 Clock Period Constraints: Multiple Stage Systems.- 3.1 Introduction.- 3.2 System Model.- 3.3 Constraints for Correct Clocking.- 3.4 Example.- 3.5 Conclusions.- 4 Exact Timing Analysis.- 4.1 Introduction.- 4.2 Motivation and Justification.- 4.3 Complexity of Problem.- 4.4 Notation and Model.- 4.5 Basic Algorithm Development.- 4.6 Conclusion.- 5 Exact Timing Analysis: Algorithm.- 5.1 Introduction.- 5.2 Algorithm Strategy.- 5.3 Calculation of Output Responses.- 5.4 Verification of Output Responses.- 5.5 Detection of Components.- 5.6 Vector Reporting.- 5.7 Implementation.- 5.8 Limitations and Extensions.- 5.9 Conclusion.- 6 Practical Considerations in Wave Pipelining.- 6.1 Architecture Choice.- 6.2 Path Delay Variation.- 6.3 Circuit Choice.- 6.4 Parametric Variations due to Manufacturing and Environmen-tal Factors.- 6.5 Clock Distribution and Physical Layout.- 6.6 Technology Scaling.- 6.7 Conclusion.- 7 Design Examples.- 7.1 Introduction.- 7.2 Parallel-Carry Adder.- 7.3 Sampler.- 7.4 Conclusion.- 8 Conclusions.- A Example Model File.- B Calculation of Tolerance of Parametric Variations.- References.

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