Overview

This book presents design techniques, analysis and implementation of high performance and power efficient, variation tolerant on-chip interconnects. Given the design paradigm shift to multi-core, interconnect-centric designs and the increase in sources of variability and their impact in sub-100nm technologies, this book will be an invaluable reference for anyone concerned with the design of next generation, high-performance electronics systems.

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9781461401308

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Introduction.- Interconnect Design Techniques.- On-Chip Wire Modeling.- Design of Delay-Insensitive Current Sensing Interconnects.- Enhancing Completion Detection Performance.- Energy Efficient Semi-Serial Interconnect.- Comparison of the Designed Interconnects.- Circuit Techniques for PVT Variation Tolerance.

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