The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits: The semi-empirical and compact model approaches
Author:   Paul Jespers
Publisher:   Springer-Verlag New York Inc.
Edition:   Previously published in hardcover
ISBN:  

9781461425052


Pages:   171
Publication Date:   03 May 2012
Format:   Paperback
Availability:   Manufactured on demand   Availability explained
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The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits: The semi-empirical and compact model approaches


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In ""The gm/ID Methodology, a Sizing Tool for Low-Voltage Analog CMOS Circuits"", we compare the semi-empirical to the compact model approach. Small numbers of parameters make the compact model attractive for the model paves the way towards analytic expressions unaffordable otherwise. The E.K.V model is a good candidate, but when it comes to short channel devices, compact models are either inaccurate or loose straightforwardness. Because sizing requires basically a reliable large signal representation of MOS transistors, we investigate the potential of the E.K.V model when its parameters are supposed to be bias dependent. The model-driven and semi-empirical methods are compared considering the Intrinsic Gain Stage and a few more complex circuits. A series of MATLAB files found on extras-springer.com  allow redoing the tests.

Full Product Details

Author:   Paul Jespers
Publisher:   Springer-Verlag New York Inc.
Imprint:   Springer-Verlag New York Inc.
Edition:   Previously published in hardcover
Dimensions:   Width: 15.50cm , Height: 1.00cm , Length: 23.50cm
Weight:   0.454kg
ISBN:  

9781461425052


ISBN 10:   1461425050
Pages:   171
Publication Date:   03 May 2012
Audience:   Professional and scholarly ,  Professional & Vocational
Format:   Paperback
Publisher's Status:   Active
Availability:   Manufactured on demand   Availability explained
We will order this item for you from a manufactured on demand supplier.

Table of Contents

Preface. Notations. Chapter 1. Sizing the Intrinsic Gain Stage. Chapter 2. The Charge Sheet Model revisited. Chapter 3. Graphical interpretation of the Charge Sheet Model. Chapter 4. Compact modeling. Chapter 5. The real transistor. Chapter 6. The real Intrinsic Gain Stage. Chapter 7. The common gate configuration. Chapter 8. Sizing the Miller Op. Amp. Annex 1. How to utilize the C.D. ROM data. Annex 2. The MATLAB toolbox. Annex 3. Temperature and Mismatch, from C.S.M. to E.K.V. Annex 4. E.K.V. intrinsic capacitance models. Bibliography. Index.

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