Overview

This thesis is written about the results of a research project the objective of which was the development of a new packet switched Network-on-Chip IIP for Multi-Processor System-on-Chip (MPSoe circuits. The selected network topology was the XGFT topology as was explained earlier. Due to the small amount of available human resources usable in this one-man project, it would have been impossible to implement a complete IIP block following all of the common design practices during the project. Another NOC with a 2-D mesh topology was also designed so as to compare it with the XGFT NOC as was explained earlier. To make the different NOCs more comparable with each other the NOCs had to be implemented with the same switch technology as will be explained later in this thesis. This design work included the development of the routing algorithms for both of the NOCs, the switch nodes, and generic NOC generators so that different NOC configurations could be generated for simulations. The performance simulations required special simulation arrangements so that appropriate comparable information of the NOCs's performance could have been achieved.

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