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OverviewThis book focusses on the spacer engineering aspects of novel MOS-based device–circuit co-design in sub-20nm technology node, its process complexity, variability, and reliability issues. It comprehensively explores the FinFET/tri-gate architectures with their circuit/SRAM suitability and tolerance to random statistical variations. Full Product DetailsAuthor: Sudeb Dasgupta (Indian Institute of Technology, Roorkee, India) , Brajesh Kumar Kaushik (Indian Institute of Technology-Roorkee, India) , Pankaj Kumar Pal (Indian Institute of Technology-Roorkee, India)Publisher: Taylor & Francis Inc Imprint: CRC Press Inc Weight: 0.378kg ISBN: 9781498783590ISBN 10: 1498783597 Pages: 154 Publication Date: 06 June 2017 Audience: College/higher education , General/trade , Tertiary & Higher Education , General Format: Hardback Publisher's Status: Active Availability: In Print This item will be ordered in for you from one of our suppliers. Upon receipt, we will promptly dispatch it out to you. For in store availability, please contact us. Table of ContentsPreface About the Authors Chapter 1 ◾ Introduction to Nanoelectronics Chapter 2 ◾ Tri-Gate FinFET Technology and Its Advancement Chapter 3 ◾ Dual-k Spacer Device Architecture and Its Electrostatics Chapter 4 ◾ Capacitive Analysis and Dual-k FinFET-Based Digital Circuit Design Chapter 5 ◾ Design Metric Improvement of a Dual-k–Based SRAM Cell Chapter 6 ◾ Statistical Variability and Sensitivity Analysis INDEXReviewsAuthor InformationSudeb Dasgupta, Brajesh Kumar Kaushik, Pankaj Kumar Pal Tab Content 6Author Website:Countries AvailableAll regions |
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