Overview

Semiconductor Memories provides in-depth coverage in the areas of design for testing, fault tolerance, failure modes and mechanisms, and screening and qualification methods including. * Memory cell structures and fabrication technologies. * Application-specific memories and architectures. * Memory design, fault modeling and test algorithms, limitations, and trade-offs. * Space environment, radiation hardening process and design techniques, and radiation testing. * Memory stacks and multichip modules for gigabyte storage.

Full Product Details

Author:   Ashok K. Sharma ,  Rochit Rajsuman
Publisher:   John Wiley & Sons Inc
Imprint:   Wiley-IEEE Press
Dimensions:   Width: 18.30cm , Height: 3.30cm , Length: 25.70cm
Weight:   1.043kg
ISBN:  

9780780310001

ISBN 10:   0780310004
Pages:   480
Publication Date:   24 September 2002
Audience:   College/higher education ,  Undergraduate
Format:   Hardback
Publisher's Status:   Active
Availability:   Out of stock  
The supplier is temporarily out of stock of this item. It will be ordered for you on backorder and shipped when it becomes available.

Table of Contents

Preface. Chapter 1: Introduction. Chapter 2: Random Access Memory Technologies. 2.1 Introduction. 2.2 Static Random Access Memories (SRAMs). 2.3 Dynamic Random Access Memories (DRAMs). Chapter 3: Nonvolatile Memories. 3.1 Introduction. 3.2 Masked Read-Only Memories (ROMs). 3.3 Programmable Read-Only Memories (PROMs). 3.4 Erasable (UV)-Programmable Read-Only Memories (EPROMs). 3.5 Electrically Erasable PROMs (EEPROMs). 3.6 Flash Memories (EPROMs or EEPROMs). Chapter 4: Memory Fault Modeling and Testing. 4.1 Introduction . . . . 4.2 RAM Fault Modeling. 4.3 RAM Electrical Testing. 4.4 RAM Pseudorandom Testing. 4.5 Megabit DRAM Testing. 4.6 Nonvolatile Memory Modeling and Testing. 4.7 IDDQ Fault Modeling and Testing. 4.8 Application Specific Memory Testing. Chapter 5: Memory Design for Testability and Fault Tolerance. 5.1 General Design for Testability Techniques. 5.2 RAM Built-in Self-Test (BIST). 5.3 Embedded Memory DFT and BIST Techniques. 5.4 Advanced BIST and Built-in Self-Repair Architectures. 5.5 DFT and BIST for ROMs. 5.6 Memory Error-Detection and Correction Techniques. 5.7 Memory Fault-Tolerance Designs. Chapter 6: Semiconductor Memory Reliability. 6.1 General Reliability Issues. 6.2 RAM Failure Modes and Mechanisms. 6.3 Nonvolatile Memory Reliability. 6.4 Reliability Modeling and Failure Rate Prediction. 6.5 Design for Reliability. 6.6 Reliability Test Structures. 6.7 Reliability Screening and Qualification. Chapter 7: Semiconductor Memory Radiation Effects. 7.1 Introduction. 7.2 Radiation Effects. 7.3 Radiation-Hardening Techniques. 7.4 Radiation Hardness Assurance and Testing. Chapter 8: Advanced Memory Technologies. 8.1 Introduction. 8.2 Ferroelectric Random Access Memories (FRAMs). 8.3 Gallium Arsenide (GaAs) FRAMs. 8.4 Analog Memories. 8.5 Magnetoresistive Random Access Memories (MRAMs). 8.6 Experimental Memory Devices. Chapter 9: High-Density Memory Packaging Technologies. 9.1 Introduction. 9.2 Memory Hybrids and MCMs (2-D). 9.3 Memory Stacks and MCMs (3-D). 9.4 Memory MCM Testing and Reliability Issues. 9.5 Memory Cards. 9.6 High-Density Memory Packaging Future Directions. Index.

Reviews

"""...a valuable reference..."" (Microelectronics Reliability, Vol. 43, 2003)"

...a valuable reference... (Microelectronics Reliability, Vol. 43, 2003)

...a valuable reference... (Microelectronics Reliability, Vol. 43, 2003)

Author Information

ASHOK K. SHARMA is the author of Semiconductor Memories: Technology, Testing, and Reliability. He is currently working as a reliability engineering manager at NASA, Goddard Space Flight Center, Greenbelt, Maryland.

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