Overview

This text should prove a useful reference for both professional and academic researchers in the field of VLSI using residue number systems. It should also be of interest to those working in the general fields of VLSI design, DSP design, and cryptography. Topics covered include: choice of moduli; architectures for conversion from binary to RNS; RNS to binary conversion techniques; quadratic RNS; and applications. Numerous examples illustrate the ideas developed. The area and computational requirements are highlighted for all designs, so the selection of a particular architecture is facilitated. Some of the topics covered have application in cryptography.

Full Product Details

Author:   P.V. Ananda Mohan
Publisher:   Springer-Verlag New York Inc.
Imprint:   Springer-Verlag New York Inc.
Edition:   2002 ed.
Volume:   677
Dimensions:   Width: 15.50cm , Height: 1.50cm , Length: 23.50cm
Weight:   1.240kg
ISBN:  

9781402070310

ISBN 10:   1402070314
Pages:   253
Publication Date:   30 April 2002
Audience:   Professional and scholarly ,  General/trade ,  Professional & Vocational
Format:   Hardback
Publisher's Status:   Active
Availability:   In Print  
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Table of Contents

1 Introduction.- 1.1 Historical survey.- 1.2 Basic definitions of RNS.- 1.3 Addition operation in RNS.- 1.4 Conclusion.- 2 Forward and Reverse Converters for General Moduli Set.- 2.1 Introduction.- 2.2 Mixed Radix Conversion based techniques.- 2.3 CRT based conversion techniques.- 2.4 Binary to RNS conversion techniques.- 2.5 Conclusion.- 3 Forward and Reverse Converters for General Moduli Set {2k-l,2k,2k+l}.- 3.1 Introduction.- 3.2 Forward conversion architectures.- 3.3 Reverse converters for the moduli set {2k-1, 2k, 2k+1}.- 3.4 Forward and Reverse converters for the moduli set{2k, 2k-l, 2k-1-l}.- 3.5 Forward and reverse converters for the moduli sets {2n+l, 2n,2n-l}.- 3.6 Conclusion.- 4 Multipliers for RNS.- 4.1 Introduction.- 4.2 Multipliers based on index calculus.- 4.3 Quarter square multipliers.- 4.4 Taylor's multipliers.- 4.5 Multipliers with in-built scaling.- 4.6 Razavi and Battelini architectures using periodic properties of residues.- 4.7 Hiasat's Modulo multipliers.- 4.8 Eueithy and Bayoumi modulo multiplication technique.- 4.9 Brickell's algorithm based multipliers and extensions.- 4.10 Stouraitis et al architectures for (A.X + B) mod mi realization.- 4.11 Multiplication using Redundant Number system.- 4.12 Conclusion.- 5 Base Extension, Scaling and Division Techniques.- 5.1 Introduction.- 5.2 Base extension and scaling techniques.- 5.3 Division in residue number systems.- 5.4 Scaling in the Moduli set {2n-1, 2n, 2n+1}.- 5.5 Conclusion.- 6 Error Detection and Correction in RNS.- 6.1 Introduction.- 6.2 Szabo and Tanaka technique for Error detection and Correction.- 6.3 Mendelbaum's Error correction technique.- 6.4 Jenkins's Error correction techniques.- 6.5 Ramachandran's Error correction technique.- 6.6 Su and Lo unified technique for scaling and error correction.- 6.7 Orto et al technique for error correction and detection using only one redundant modulus.- 6.8 Conclusion.- 7 Quadratic Residue Number Systems.- 7.1 Introduction.- 7.2 Basic operations in QRNS.- 7.3 Modified quadratic residue number systems.- 7.4 Jenkins and Krogmeier implementations.- 7.5 Taylor's single modulus ALU for QRNS.- 7.6 Conclusion.- 8 Applications of Residue Number Systems.- 8.1 Introduction.- 8.2 Digital Analog Converters.- 8.3 FIR Filters.- 8.4 Recursive RNS filter implementation.- 8.5 Digital frequency synthesis using RNS.- 8.6 Multiple Valued Logic Based RNS designs.- 8.7 Paliouras and Stouraitis architectures using moduli of the form rn.- 8.8 Taheri, Jullien and Miller technique of High-speed computation in rings using systolic Architectures.- 8.9 RNS based implementation of FFT structures.- 8.10 Optimum Symmetric Residue Number System.- 8.11 Conclusion.- 9 References.

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