Overview

This manual is a comprehensive reference describing the implementation-specific interfaces and architectural features of the highly-integrated 64-bit R4000 and R4400 MIPS RISC processors. This manual also describes the MIPS RISC instruction Set Architecture (ISA), including the 64-bit extensions of the ISA.

Full Product Details

Author:   Silicon Graphics, Inc.
Publisher:   Pearson Education (US)
Imprint:   Prentice Hall
Dimensions:   Width: 23.40cm , Height: 2.90cm , Length: 17.80cm
Weight:   1.052kg
ISBN:  

9780131059252

ISBN 10:   0131059254
Pages:   752
Publication Date:   01 July 1993
Audience:   College/higher education ,  Tertiary & Higher Education
Format:   Paperback
Publisher's Status:   Out of Print
Availability:   Out of stock  

Table of Contents

 1. Introduction.  2. CPU Instruction Set Summary.  3. The CPU Pipeline.  4. Memory Management.  5. CPU Exception Processing.  6. Floating-Point Unit.  7. Floating-Point Exceptions.  8. R4000 Processor Signal Descriptions.  9. Initialization Interface. 10. Clock Interface. 11. Cache Organization, Operation, and Coherency. 12. System Interface. 13. Secondary Cache Interface. 14. JTAG Interface. 15. R4000 Processor Interrupts. 16. Error Checking and Correcting. Appendix A: CPU Instruction Set Details. Appendix B: FPU Instruction Set Details. Appendix C: Subblock Ordering. Appendix D: Output Buffer …Di/…Dt Control Mechanism. Appendix E: PLL Passive Components. Appendix F: R4000 Coprocessor 0 Hazards.

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Author Information

Joe Heinrich is a staff technical writer at Silicon Graphics, Inc. Previously he held similar positions at MIPS Computers, Sun Microsystems, and Xerox PARC.

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