Low Power Design with High-Level Power Estimation and Power-Aware Synthesis
Author:   Sumit Ahuja ,  Avinash Lakshminarayana ,  Sandeep Kumar Shukla
Publisher:   Springer-Verlag New York Inc.
Edition:   2012 ed.
ISBN:  

9781489987808


Pages:   170
Publication Date:   23 October 2014
Format:   Paperback
Availability:   Manufactured on demand   Availability explained
We will order this item for you from a manufactured on demand supplier.

Our Price $290.37 Quantity:  
Add to Cart

Share |

Low Power Design with High-Level Power Estimation and Power-Aware Synthesis


Add your own review!

Overview

This book presents novel research techniques, algorithms, methodologies and experimental results for high level power estimation and power aware high-level synthesis. Readers will learn to apply such techniques to enable design flows resulting in shorter time to market and successful low power ASIC/FPGA design.

Full Product Details

Author:   Sumit Ahuja ,  Avinash Lakshminarayana ,  Sandeep Kumar Shukla
Publisher:   Springer-Verlag New York Inc.
Imprint:   Springer-Verlag New York Inc.
Edition:   2012 ed.
Dimensions:   Width: 15.50cm , Height: 1.00cm , Length: 23.50cm
Weight:   0.454kg
ISBN:  

9781489987808


ISBN 10:   1489987800
Pages:   170
Publication Date:   23 October 2014
Audience:   Professional and scholarly ,  Professional & Vocational
Format:   Paperback
Publisher's Status:   Active
Availability:   Manufactured on demand   Availability explained
We will order this item for you from a manufactured on demand supplier.
Language:   English

Table of Contents

Introduction.- Related Work.- Background.- Architectural Selection using High Level Synthesis.- Statistical Regression Based Power Models.- Coprocessor Design Space Exploration Using High Level Synthesis.- Regression-based Dynamic Power Estimation for FPGAs.- High Level Simulation Directed RTL Power Estimation.- Applying Verification Collaterals for Accurate Power Estimation.- Power Reduction using High-Level Clock-gating.- Model-Checking to exploit Sequential Clock-gating.- System Level Simulation Guided Approach for Clock-gating.- Conclusions.

Reviews

Author Information

Tab Content 6

Author Website:  

Customer Reviews

Recent Reviews

No review item found!

Add your own review!

Countries Available

All regions
Latest Reading Guide

MRG2025CC

 

Shopping Cart
Your cart is empty
 Shopping cart
Mailing List

 

Sign up now