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OverviewThe goal of Leakage in Nanometer CMOS Technologies is to provide ample detail so that the reader can understand why leakage power components are becoming increasingly relevant in CMOS systems that use nanometer scale MOS devices. Leakage current sources at the MOS device level including sub-threshold and different types of tunneling are discussed in detail. The book covers promising solutions at the device, circuit, and architecture levels of abstraction. Manifestation of these MOS device leakage components at the full chip level depends considerably on several aspects including the nature of the circuit block, its state, its application workload, and Process/Voltage/Temperature conditions. The sensitivity of the various MOS leakage sources to these conditions are described from the first principles. The resulting manifestations are discussed at length to help the reader understand the effectiveness of leakage power reduction solutions under these different conditions. Case studies are presented to highlight real world examples that reap the benefits of leakage power reduction solutions.; Finally, the book highlights different device design choices that exist to mitigate increases in the leakage components as technology scales. Full Product DetailsAuthor: Anantha Chandrakasan , Siva G NarendraPublisher: Springer Imprint: Springer ISBN: 9786610616589ISBN 10: 6610616582 Pages: 310 Publication Date: 01 January 2006 Audience: General/trade , General Format: Electronic book text Publisher's Status: Active Availability: Out of stock ![]() The supplier is temporarily out of stock of this item. It will be ordered for you on backorder and shipped when it becomes available. Table of ContentsReviewsAuthor InformationTab Content 6Author Website:Countries AvailableAll regions |