Introduction to VLSI Design Flow

Author:   Sneh Saurabh (Indraprastha Institute of Information Technology, Delhi )
Publisher:   Cambridge University Press
ISBN:  

9781009200813


Pages:   714
Publication Date:   15 June 2023
Format:   Paperback
Availability:   Manufactured on demand   Availability explained
We will order this item for you from a manufactured on demand supplier.

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Introduction to VLSI Design Flow


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Full Product Details

Author:   Sneh Saurabh (Indraprastha Institute of Information Technology, Delhi )
Publisher:   Cambridge University Press
Imprint:   Cambridge University Press
Dimensions:   Width: 18.30cm , Height: 2.80cm , Length: 24.10cm
Weight:   0.960kg
ISBN:  

9781009200813


ISBN 10:   100920081
Pages:   714
Publication Date:   15 June 2023
Audience:   General/trade ,  General
Format:   Paperback
Publisher's Status:   Active
Availability:   Manufactured on demand   Availability explained
We will order this item for you from a manufactured on demand supplier.

Table of Contents

Part I. Overview of VLSI Design Flow: Chapter 1. Foundation; Chapter 2. Introduction to Integrated Circuits; Chapter 3. Pre-RTL Methodologies; Chapter 4. RTL to GDS Implementation Flow; Chapter 5. Verification Techniques; Chapter 6. Testing Techniques; Chapter 7. Post-GDS Processes; Part II. Logic Design: Chapter 8. Modeling Hardware using Verilog; Chapter 9. Simulation-based Verification; Chapter 10. RTL Synthesis; Chapter 11. Formal Verification, Chapter 12. Logic Optimization; Chapter 13. Technology Library; Chapter 14. Static Timing Analysis; Chapter 15. Constraints; Chapter 16. Technology Mapping; Chapter 17. Timing-driven Optimizations; Chapter 18. Power Analysis; Chapter 19. Power-driven Optimizations; Part III. Design for Testability (DFT): Chapter 20. Basics of DFT; Chapter 21. Scan Design; Chapter 22. Automatic Test Pattern Generation (ATPG); Chapter 23. Built-in Self-test (BIST); Part IV. Physical Design: Chapter 24. Basic Concepts for Physical Design; Chapter 25. Chip Planning; Chapter 26. Placement; Chapter 27. Clock Tree Synthesis (CTS); Chapter 28. Routing; Chapter 29. Physical Verification and Signoff; Chapter 30. Post-silicon Validation.

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Author Information

Sneh Saurabh is Associate Professor at the Department of Electronics and Communication Engineering at the Indraprastha Institute of Information Technology, New Delhi, India. He has rich experience in the semiconductor industry, having spent sixteen years working for industry leaders such as Cadence Design Systems, Synopsys India, and Magma Design Automation. His research interests include VLSI design and automation, nanoelectronics, and energy-efficient systems.

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