Overview

This book presents the thoroughly refereed post-proceedings of the Second International Workshop on Intelligent Memory Systems, IMS 2000, held in Cambridge, MA, USA, in November 2000. The nine revised full papers and six poster papers presented were carefully reviewed and selected from 28 submissions. The papers cover a wide range of topics in intelligent memory computing; they are organized in topical sections on memory technology, processor and memory architecture, applications and operating systems, and compiler technology.

Full Product Details

Author:   Frederic T. Chong ,  Christoforos Kozyrakis ,  Mark Oskin
Publisher:   Springer-Verlag Berlin and Heidelberg GmbH & Co. KG
Imprint:   Springer-Verlag Berlin and Heidelberg GmbH & Co. K
Edition:   2001 ed.
Volume:   2107
Dimensions:   Width: 15.50cm , Height: 1.10cm , Length: 23.50cm
Weight:   0.660kg
ISBN:  

9783540423287

ISBN 10:   3540423281
Pages:   196
Publication Date:   29 August 2001
Audience:   Professional and scholarly ,  Professional & Vocational
Format:   Paperback
Publisher's Status:   Active
Availability:   In Print  
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Table of Contents

Memory Technology.- A 64Mbit Mesochronous Hybrid Wave Pipelined Multibank DRAM Macro.- Software Controlled Reconfigurable On-chip Memory for High Performance Computing.- Processor and Memory Architecture.- Content-Based Prefetching: Initial Results.- Memory System Support for Dynamic Cache Line Assembly.- Adaptively Mapping Code in an Intelligent Memory Architecture.- Applications and Operating Systems.- The Characterization of Data Intensive Memory Workloads on Distributed PIM Systems?.- Memory Management in a PIM-Based Architecture.- Compiler Technology.- Exploiting On-chip Memory Bandwidth in the VIRAM Compiler.- FlexCache: A Framework for Flexible Compiler Generated Data Caching.- Poster Session.- Aggressive Memory-Aware Compilation.- Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips?.- SAGE: A New Analysis and Optimization System for FlexRAM Architecture.- Performance/Energy Efficiency of Variable Line-Size Caches for Intelligent Memory Systems.- The DIVA Emulator: Accelerating Architecture Studies for PIM-Based Systems.- Compiler-Directed Cache Line Size Adaptivity ?.- Summary of Question/Answer Sessions for Workshop Presentations.

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