Free Delivery Over $100
|
|
|||
|
||||
OverviewIndex generation functions are binary-input integer valued functions. They represent functions of content addressable memories (CAMs). Applications include: IP address tables; terminal controllers; URL lists; computer virus scanning circuits; memory patch circuits; list of English words; code converters; and pattern matching circuits.This book shows memory-based realization of index generation functions. It shows: methods to implement index generation functions by look-up table (LUT) cascades and index generation units (IGU), methods to reduce the number of variables using linear transformations, and methods to estimate the sizes of memories, with many illustrations, tables, examples, exercises, and their solutions. Full Product DetailsAuthor: Tsutomu Sasao , Mitchell A. ThorntonPublisher: Morgan & Claypool Publishers Imprint: Morgan & Claypool Publishers ISBN: 9781681736778ISBN 10: 1681736772 Pages: 183 Publication Date: 30 October 2019 Audience: Professional and scholarly , Professional & Vocational Format: Hardback Publisher's Status: Active Availability: In Print  This item will be ordered in for you from one of our suppliers. Upon receipt, we will promptly dispatch it out to you. For in store availability, please contact us. Table of ContentsPreface Acknowledgments Introduction Applications Definitions and Basic Properties Index Generation Functions and Their Realizations Minimization of Primitive Variables Linear Transformations of Input Variables Iterative Reduction of Compound Variables Irreducible Index Generation Function SAT-Based Method to Find Linear Transformations Statistical Approach Realization Using Four IGUs References on Index Generation Functions Conclusions Bibliography Author's Biography IndexReviewsAuthor InformationTsutomu Sasao received B.E., M.E., and Ph.D. degrees in Electronics Engineering from Osaka University, Osaka Japan, in 1972, 1974, and 1977, respectively. He has held faculty/research positions at Osaka University, Japan; IBM T. J. Watson Research Center, Yorktown Height, NY; the Naval Postgraduate School, Monterey, CA; and Kyushu Institute of Technology, Iizuka, Japan. Now, he is a Professor of Department of Computer Science, Meiji University, Kawasaki, Japan. His research areas include logic design and switching theory, representations of logic functions, and multiple-valued logic. He has published more than 10 books on logic design including, Logic Synthesis and Optimization (1993), Representation of Discrete Functions (1996), Switching Theory for Logic Synthesis (1999), Logic Synthesis and Verification (2002), Progress in Applications of Boolean Functions (2010), Memory-Based Logic Synthesis (2011), and Applications of Zero-suppressed Decision Diagrams (2015). He has served Program Chairman for the IEEE International Symposium on Multiple-Valued Logic (ISMVL) many times. Also, he was the Symposium Chairman of the 28th ISMVL held in Fukuoka, Japan in 1998. He received the NIWA Memorial Award in 1979, Takeda Techno-Entrepreneurship Award in 2001, and Distinctive Contribution Awards from IEEE Computer Society MVL-TC for papers presented at ISMVLs in 1986, 1996, 2003, 2004, 2013, and 2018. He has served an associate editor of the IEEE Transactions on Computers. He is a Life Fellow of the IEEE. Tab Content 6Author Website:Countries AvailableAll regions |
||||
