Overview

Tran et al. (2005) proposed a power estimation model for digital CMOS circuits. The circuit was divided into five sections and the power dissipation of each part has been estimated individually. Further the implemented gates were also counted, the proposed power investigation model suggest early guidelines for design of circuits. The leakage power estimation is most important factor the study of design feasibility. Derakhshandeh et al. (2005) identified the relationship between the leakage power and threshold voltage, where initially the number of input gates were identified, followed by identifying the number of inputs to the gates and their corresponding states. The predicted results on benchmark ICs reported improved accuracy than the conventional methods of estimation. Ligang et al. (2006) introduced neural network models for power estimation for VLSI circuits. In the proposed study the authors used ISCAS89 benchmark circuits and the corresponding experimental results were noted. The neural network based power estimation techniques produced better results as compared to the conventional methods such as Monte-Carlo and other statistical techniques. A linear programming based leakage power estimation technique has been proposed by Chen et al. (2006), where Genetic Algorithm was implemented for Minimum Leakage Vector (MLV) searching, the leakage power is estimated on gate level by linear programming method. The study assists in reducing the leakage power of VLSI circuits with easy implementations. Chaudhry et al. (2006) presented accurate power estimation strategy by extracting the switching and clock activity of macro power models. Do et al. (2007) discussed a high power estimation models for proposed 2-kB 6T - SRAM array, in the proposed study the authors computed the threshold leakage by combining the probing methodology. The memory

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