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OverviewHigh-Speed Clock Network Design is a collection of design concepts, techniques and research works from the author for clock distribution in microprocessors and high-performance chips. It is organized in 11 chapters. Full Product DetailsAuthor: Qing K. ZhuPublisher: Springer-Verlag New York Inc. Imprint: Springer-Verlag New York Inc. Edition: Softcover reprint of hardcover 1st ed. 2003 Weight: 0.454kg ISBN: 9781441953360ISBN 10: 1441953361 Pages: 188 Publication Date: 02 December 2010 Audience: Professional and scholarly , Professional & Vocational Format: Paperback Publisher's Status: Active Availability: Out of stock ![]() The supplier is temporarily out of stock of this item. It will be ordered for you on backorder and shipped when it becomes available. Table of Contents1 Introduction.- 2 Overview to Timing Constraints.- 3 Sequential Clocked Elements.- 4 Design Methodology for Domino Circuits.- 5 Clock Generation and De-Skewing.- 6 Microprocessor Clock Distribution Examples.- 7 Clock Network Simulation Methods.- 8 Low-Voltage Swing Clock Distribution.- 9 Routing Clock on Package.- 10 Balanced Clock Routing Algorithms.- 11 Clock Tree Design Flow in Asic.- Reference.ReviewsAuthor InformationTab Content 6Author Website:Countries AvailableAll regions |