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Author:   James Reinders (Director and Programming Model Architect, Intel Corporation) ,  James Jeffers (Principal Engineer and Visualization Lead, Intel Corporation) ,  James Reinders (Director and Programming Model Architect, Intel Corporation) ,  James Reinders (Director and Programming Model Architect, Intel Corporation)
Publisher:   Elsevier Science & Technology
Imprint:   Morgan Kaufmann Publishers In
Dimensions:   Width: 19.10cm , Height: 2.50cm , Length: 23.50cm
Weight:   1.090kg
ISBN:  

9780128021187

ISBN 10:   0128021187
Pages:   600
Publication Date:   07 November 2014
Audience:   Professional and scholarly ,  Professional & Vocational
Format:   Paperback
Publisher's Status:   Active
Availability:   Manufactured on demand  
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Table of Contents

1. Introduction 2. Towards an efficient Godunov's scheme  on Phi 3. Better Concurrency and SIMD on HBM 4. Case Study: Analyzing and Optimizing Concurrency 5. Plesiochronous Phasing Barriers 6. Parallel Evaluation of Fault Tree Expressions 7. Deep-learning and Numerical Optimization 8. Optimizing Gather/Scatter Patterns 9. A many core implementation of the direct N-body problem 10. N-body Methods on Intel® Xeon Phi™ Coprocessors 11. Dynamic Load Balancing using OpenMP 4.0 12. Concurrent Kernel Offloading 13. Heterogeneous Computing with MPI 14. Power Analysis on the Intel® Xeon Phi™ Coprocessor 15. Integrating Intel Xeon Phis into a Cluster 16. Native File systems 17. NWChem: Quantum Chemistry Simulations at Scale 18. Efficient nested parallelism on large scale system 19. Performance optimization of Black-Scholes pricing 20. Host and Coprocessor Data Transfer through the COI 21. High Performance Ray Tracing with Embree 22. Portable and Perform with OpenCL 23. Characterization and Auto-tuning of 3DFD. 24. Profiling-guided optimization of cache performance 25. Heterogeneous MPI optimization with ITAC 26. Scalable Out-of-core Solvers on a Cluster 27. Sparse matrix-vector multiplication: parallelization and vectorization 28. Morton Order Improves Performance

Reviews

This book will make it much easier in general to exploit high levels of parallelism including programming optimally for the Intel Xeon Phi products. The common programming methodology between the Xeon and Xeon Phi families is good news for the entire scientific and engineering community; the same programming can realize parallel scaling and vectorization for both multicore and many-core. --from the Foreword by Sverre Jarp, CERN Openlab CTO

This book will make it much easier in general to exploit high levels of parallelism including programming optimally for the Intel Xeon Phi products. The common programming methodology between the Xeon and Xeon Phi families is good news for the entire scientific and engineering community; the same programming can realize parallel scaling and vectorization for both multicore and many-core. - from the Foreword by Sverre Jarp, CERN Openlab CTO

Author Information

James Reinders is a senior engineer who joined Intel Corporation in 1989 and has contributed to projects including the world’s first TeraFLOP supercomputer (ASCI Red), as well as compilers and architecture work for a number of Intel processors and parallel systems. James has been a driver behind the development of Intel as a major provider of software development products, and serves as their chief software evangelist. James has published numerous articles, contributed to several books and is widely interviewed on parallelism. James has managed software development groups, customer service and consulting teams, business development and marketing teams. James is sought after to keynote on parallel programming, and is the author/co-author of three books currently in print including Structured Parallel Programming, published by Morgan Kaufmann in 2012. Jim Jeffers was the primary strategic planner and one of the first full-time employees on the program that became Intel ® MIC. He served as lead SW Engineering Manager on the program and formed and launched the SW development team. As the program evolved, he became the workloads (applications) and SW performance team manager. He has some of the deepest insight into the market, architecture and programming usages of the MIC product line. He has been a developer and development manager for embedded and high performance systems for close to 30 years.

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