Overview

Hardware trojans - which involve malicious modification of integrated circuits (ICs) during the design or fabrication stage - can give access to sensitive information, deny service, and so on. They can be difficult to detect but have serious consequences for the security of the IC. Exploring hardware trojan attacks and their countermeasures using high level synthesis (HLS), this book covers different attack strategies, their detection and countermeasures, as well as future risks. The expert author presents key information on hardware trojan attacks and their countermeasures. The book is split into four parts, starting with an introduction to hardware trojans and high-level synthesis, and then looking at various attack strategies. This is then followed by information on detection (a key issue in hardware trojan security), and countermeasures. The book finishes by looking at additional concerns and future directions of this key area in hardware security. Readers will learn about topics such as hardware trojan classification and taxonomy, trojan attacks using malicious HLS framework, time bomb HLS-based hardware trojan attacks, trojan attacks on ML accelerator designs, other payloads of HLS trojan attack, trojan detection technique using DMR, and trojan detection and isolation technique and compromising IP designs via malicious exploitation of commercial CAD-HLS tools. High-Level Synthesis Hardware Trojan Attacks and Countermeasures is a key resource for researchers and engineers working in hardware security and chip design.

Full Product Details

Author:   Anirban Sengupta (Full Professor, Indian Institute of Technology (IIT) Indore, India)
Publisher:   Institution of Engineering and Technology
Imprint:   Institution of Engineering and Technology
ISBN:  

9781807050672

ISBN 10:   180705067
Pages:   250
Publication Date:   01 June 2026
Audience:   College/higher education ,  Professional and scholarly ,  Tertiary & Higher Education ,  Professional & Vocational
Format:   Hardback
Publisher's Status:   Forthcoming
Availability:   Not yet available  
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Table of Contents

Part I: Foundations Chapter 1: Introduction to Hardware Trojans and High-Level Synthesis Part II: Attack Strategies Chapter 2: Trojan Attacks via Malicious HLS Framework Chapter 3: Time Bomb HLS-based Hardware Trojan Attack for Performance Degradation Chapter 4: Hardware Trojan Attacks on HLS based Machine Learning Accelerators Chapter 5: Power Exhaustion Attacks in HLS Part III: Detection and Countermeasures Chapter 6: Machine Learning-based Detection of HLS Trojans Chapter 7: HLS Trojan Detection using Dual Modular Redundancy (DMR) Techniques Chapter 8: Trojan-Resistant IP Designs and Isolation Strategies Part IV: Additional Perspectives Chapter 9: Compromising IP Designs via Malicious Exploitation of Commercial CAD-HLS Tools Vs. Backdoor Trojan-inserted HLS Frameworks Chapter 10: Conclusion and Future Direction

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Author Information

Anirban Sengupta is a full professor at the Indian Institute of Technology (IIT) Indore, India. He has more than 340 publications and patents, including 7 books, to his credit. He is a fellow of the IET, the British Computer Society, and IETE, and has been awarded the IEEE Chester Sall Memorial Consumer Electronics, IEEE Distinguished Visitor, and IEEE CESoc Outstanding Editor Award.

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