Hardware and Software: Verification and Testing: 10th International Haifa Verification Conference, HVC 2014, Haifa, Israel, November 18-20, 2014, Proceedings

Author:   Eran Yahav
Publisher:   Springer International Publishing AG
Edition:   2014 ed.
Volume:   8855
ISBN:  

9783319133379


Pages:   302
Publication Date:   06 November 2014
Format:   Paperback
Availability:   Manufactured on demand   Availability explained
We will order this item for you from a manufactured on demand supplier.

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Hardware and Software: Verification and Testing: 10th International Haifa Verification Conference, HVC 2014, Haifa, Israel, November 18-20, 2014, Proceedings


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Author:   Eran Yahav
Publisher:   Springer International Publishing AG
Imprint:   Springer International Publishing AG
Edition:   2014 ed.
Volume:   8855
Dimensions:   Width: 15.50cm , Height: 1.70cm , Length: 23.50cm
Weight:   4.861kg
ISBN:  

9783319133379


ISBN 10:   3319133373
Pages:   302
Publication Date:   06 November 2014
Audience:   Professional and scholarly ,  Professional & Vocational
Format:   Paperback
Publisher's Status:   Active
Availability:   Manufactured on demand   Availability explained
We will order this item for you from a manufactured on demand supplier.

Table of Contents

Using Coarse-Grained Abstractions to Verify Linearizability on TSO Architectures.- Enhancing Scenario Quality Using Quasi-Events.- Combined Bounded and Symbolic Model Checking for Incomplete Timed Systems.- DynaMate: Dynamically Inferring Loop Invariants for Automatic Full Functional Verification.- Generating Modulo-2 Linear Invariants for Hardware Model Checking.- Suraq — A Controller Synthesis Tool Using Uninterpreted Functions.- Synthesizing Finite-State Protocols from Scenarios and Requirements.- Automatic Error Localization for Software Using Deductive Verification.- Generating JML Specifications from Alloy Expressions.- Assume-Guarantee Abstraction Refinement Meets Hybrid Systems.- Handling TSO in Mechanized Linearizability Proofs.- Partial Quantifier Elimination.- Formal Verification of 800 Genetically Constructed Automata Programs: A Case Study.- A Framework to Synergize Partial Order Reduction with State Interpolation.- Reduction of Resolution Refutations and Interpolants via Subsumption.- Read, Write and Copy Dependencies for Symbolic Model Checking.- Efficient Combinatorial Test Generation Based on Multivalued Decision Diagrams.- Formal Verification of Secure User Mode Device Execution with DMA.- Supervisory Control of Discrete-Event Systems via IC3.- Partial-Order Reduction for Multi-core LTL Model Checking.- A Comparative Study of Incremental Constraint Solving Approaches in Symbolic Execution.

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