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This dissertation, Geometric Programming and Signal Flow Graph Assisted Design of Interconnect and Analog Circuits by 張永泰, Wing-tai, Cheung, was obtained from The University of Hong Kong (Pokfulam, Hong Kong) and is being sold pursuant to Creative Commons: Attribution 3.0 Hong Kong License. The content of this dissertation has not been altered in any way. We have altered the formatting in order to facilitate the ease of printing and reading of the dissertation. All rights not granted by the above license are retained by the author. Abstract: Abstract of thesis entitled Geometric Programming and Signal Flow Graph Assisted Design of Interconnect and Analog Circuits Submitted by CHEUNG, Wing Tai for the degree of Master of Philosophy at the University of Hong Kong in August 2007 Very-large-scale integration (VLSI) interconnects and analog circuits play an impor- tant role in modern integrated circuit (IC) development. To ensure the IC design meets the time-to-market with viable production cost, the design stages are relying more heav- ily on computer-aided design (CAD) automation. Employing fast and global optimization techniques in the design stage constitutes a versatile way to facilitate the best circuit per- formance within a fast design cycle. This thesis features two main techniques, namely Geometric Programming (GP) and Signal Flow Graph (SFG), which assist the design of electronic circuits. First, the power op- timization of a repeater-inserted interconnects using GP is investigated. The ever-shrinking interconnect sizes and the quest for high-speed VLSI circuits have posed significant chal- lenges to the design of interconnect wires. Motivated by this problem, an automated design flow utilizing GP optimization is proposed for repeater insertion under power dissipation constraints. Furthermore, the development of low-noise amplifiers (LNAs) using the GP framework is proposed. The objective of this optimization approach is to minimize the noise figure of an LNA, subject to resonant frequency and input impedance matching. Byemploying the common source inductive degenerated LNA, globally optimal circuits satis- fying design constraints and specifications are obtained with high computational efficiency. An enhancement of the proposed automated design flow with linearity constraints made possible by monomial curve fitting technique, thus conforming to the GP standard form and allowing its fast deployment, is also introduced. The second part of this thesis addresses graphical-assisted design in electronic circuits. First, a parallel switched-capacitor resonant converter (SCRC) structure which fully uti- lizes the pulse switching period through interleaving technique is proposed. Signal Flow Graph (SFG) is utilized for the design of SCRC. The operations of the power converters and the directions of signal flow are visualized and analyzed using flow graph techniques. Conversion of the graphical representation to mathematical representation, such as transfer function, uses the Mason Rule. The proposed SCRC architecture demonstrates an excellent efficiency and load regulation, which are then verified using PSPICE simulations. An abstract of exactly 329 words DOI: 10.5353/th_b3955852 Subjects: Geometric programmingElectronic circuit designIntegrated circuits - Very large scale integration

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