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OverviewFormal Verification: An Essential Toolkit for Modern VLSI Design, Second Edition presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification (FV) enables a designer to directly analyze and mathematically explore the quality or other aspects of a Register Transfer Level (RTL) design without using simulations. This can reduce time spent validating designs and more quickly reach a final design for manufacturing. Building on a basic knowledge of SystemVerilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes. Every chapter in the second edition has been updated to reflect evolving FV practices and advanced techniques. In addition, a new chapter, Formal Signoff on Real Projects, provides guidelines for implementing signoff quality FV, completely replacing some simulation tasks with significantly more productive FV methods. After reading this book, readers will be prepared to introduce FV in their organization to effectively deploy FV techniques that increase design and validation productivity. Full Product DetailsAuthor: Erik Seligman (Senior Product Engineering Architect, Cadence Design Systems, Wichita, Kansas, USA) , Tom Schubert (Adjunct Professor, Department of Electrical and Computer Engineering, Portland State University, Portland, OR, USA) , M. V. Achutha Kiran Kumar (Intel Fellow, Formal Verification Central Technology Office, Intel, Bangalore, India)Publisher: Elsevier Science & Technology Imprint: Morgan Kaufmann Edition: 2nd edition Weight: 0.880kg ISBN: 9780323956123ISBN 10: 0323956122 Pages: 424 Publication Date: 26 May 2023 Audience: Professional and scholarly , Professional & Vocational Format: Paperback Publisher's Status: Active Availability: Manufactured on demand We will order this item for you from a manufactured on demand supplier. Table of ContentsReviewsAuthor InformationErik Seligman is currently a Senior Product Engineering Architect at Cadence Design Systems, where he helps to plan and support the Jasper Formal Verification tool suite. Previously he worked at Intel Corporation in Hillsboro, Oregon for over two decades, in a variety of positions involving software, design, simulation, and formal verification. In his spare time he hosts the “Math Mutation podcast, and has served as an elected director on the Hillsboro school board. Tom Schubert is on the Electrical and Computer Engineering faculty at Portland State University and directs a graduate track in Design Verification and Validation. Previously, he was at Intel Corporation for 17 years in Hillsboro, Oregon, where he managed Intel's largest pre-silicon validation formal verification team develop and apply FPV techniques on multiple generations of microprocessor designs. Tom received a PhD in Computer Science from the University of California, Davis. M. V. Achutha Kiran Kumar is an Intel Fellow in the Design Engineering group at Intel and leads the company’s Formal Verification Central Technology Office, one of the largest industrial Formal Verification teams in the world. He has over 20 years experience where he worked in various areas of the chip design cycle which includes RTL design, structural design, circuit design, simulation, and various levels of validation including formal verification. Tab Content 6Author Website:Countries AvailableAll regions |