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OverviewI wrote this for engineers who need to make many CPUs cooperate concurrently. I start from first principles of cache coherence and the C memory model, then build up atomics and fences that withstand both compiler and hardware reordering. I examine interrupts, preemption, and execution contexts that compete for the same data, then develop a toolbox of synchronization primitives including spinlocks, mutexes, reader-writer locks, RCU, and sequence counters. Each mechanism is presented with invariants, failure modes, progress guarantees, and guidance on when to use it. I then construct a practical scheduler and its ecosystem. You will see per-CPU runqueues, wakeups, timers, and load balancing for SMP and NUMA, along with affinity, migration, IPIs, TLB shootdowns, deferred work, and futex-based wait-wake paths. I address priority inversion, deadlocks, livelocks, and false sharing, and I include lock-free structures with safe reclamation. The goal is simple and measurable: predictable concurrency, low tail latency, and strong throughput in a kernel written in C. Full Product DetailsAuthor: M ShorPublisher: Independently Published Imprint: Independently Published Volume: 3 Dimensions: Width: 15.20cm , Height: 2.20cm , Length: 22.90cm Weight: 0.562kg ISBN: 9798269657103Pages: 424 Publication Date: 13 October 2025 Audience: General/trade , General Format: Paperback Publisher's Status: Active Availability: Available To Order We have confirmation that this item is in stock with the supplier. It will be ordered in for you and dispatched immediately. Table of ContentsReviewsAuthor InformationTab Content 6Author Website:Countries AvailableAll regions |
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