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This dissertation, Estimation of the Impact of Patterning Error on MOSFET by Conformal Mapping by Chiu-ho, Pun, 潘昭豪, was obtained from The University of Hong Kong (Pokfulam, Hong Kong) and is being sold pursuant to Creative Commons: Attribution 3.0 Hong Kong License. The content of this dissertation has not been altered in any way. We have altered the formatting in order to facilitate the ease of printing and reading of the dissertation. All rights not granted by the above license are retained by the author. Abstract: Abstract of thesis entitled Estimation of the Impact of Patterning Error on MOSFET by Conformal Mapping Submitted by Pun Chiu Ho (1999119129) for the degree of Master of Philosophy at The University of Hong Kong in Aug 2004 During IC fabrication, layout shapes of devices and circuits do not exactly replicate onto wafers due to distortions in pattern-transfer processes. As the dimensions of devices shrink, the effects of these patterning errors on the circuits become increasingly significant, and so there is an increasing need to consider these process-induced patterning errors. In order to assess the impact of patterning error in the design stage, conformal mapping is used to provide a simple model for estimating the effects of the distortion on the I-V characteristics of MOSFETs. The method is verified by a first-order partial differential equation model and also by the 3D device simulator DAVINCI, which can include the secondary effects of MOSFET. The impact of pattern distortion in MOSFET on circuit performance is also examined by the proposed model. The conformal- mapping model matches the first-order model well. However, it has some error in the verification with the device simulator, due to the secondary physical effects of MOSFET. Some approaches for choosing the channel dimensions are also studied in this work with a view to minimizing the error, and they show roughly the same accuracy. The conformal-mapping model is therefore proved suitable for estimating the impact of patterning error on the MOSFETs of well-designed IC processes in the design stage. The speed of the conformal-mapping method is determined by the number of nodes required for each MOSFET and the complexity of its channel shape, and the model can generally provide a faster estimation than a device simulator. (254 words) DOI: 10.5353/th_b3073083 Subjects: Integrated circuits - TestingConformal mappingIntegrated circuits - Design and constructionSemiconductors - Design and construction

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