Overview

This book lays out the concepts necessary to understand how a computer works. For reasons of clarity, the authors have deliberately chosen examples that apply to machines from all eras, without having to water down the contents of the book. This choice helps to show how techniques, concepts and performances have evolved since the first computers. The book is divided into five parts. The first four, which are of increasing difficulty, are the core of the book: “Elements of a Basic Architecture”, “Programming Model and Operation”, “Memory Hierarchy”, “Parallelism and Performance Enhancement”. The final part provides hints and solutions to the exercises in the book as well as appendices. The reader may approach each part independently based on their prior knowledge and goals.

Full Product Details

Author:   Gérard Blanchet ,  Bertrand Dupouy
Publisher:   ISTE Ltd and John Wiley & Sons Inc
Imprint:   ISTE Ltd and John Wiley & Sons Inc
Dimensions:   Width: 16.10cm , Height: 2.70cm , Length: 24.00cm
Weight:   0.708kg
ISBN:  

9781848214293

ISBN 10:   1848214294
Pages:   380
Publication Date:   18 December 2012
Audience:   Professional and scholarly ,  Professional & Vocational
Format:   Hardback
Publisher's Status:   Active
Availability:   Out of stock  
The supplier is temporarily out of stock of this item. It will be ordered for you on backorder and shipped when it becomes available.

Table of Contents

Preface xiii Part 1. Elements of a Basic Architecture 1 Chapter 1. Introduction 3  1.1. Historical background 3  1.2. Introduction to internal operation 13  1.3. Future prospects 15 Chapter 2. The Basic Module 17  2.1. Memory 17  2.2. The processor 20  2.3. Communication between modules 30 Chapter 3. The Representation of Information 35    3.1 Review 36  3.2. Number representation conventions 38  3.3. Character representation 48  3.4 Exercises 52 Part 2. Programming Model and Operations 55 Chapter 4. Instructions 57  4.1. Programming model 58  4.2 The set of instructions 62  4.3. Programming examples 68  4.4. From assembly language to basic instructions 70 Chapter 5. The Processor 74  5.1. The control bus 76  5.2. Execution of the instruction 79  5.3. Sequencer composition 87  5.4. Extensions 91  5.5. Exercise 101 Chapter 6. Inputs and Outputs 103  6.1. Examples 105  6.2. Design and addressing of EU 115  6.3. Exchange modes 118  6.4. Handling interrupts 127  6.5. Exercises 133 Part 3. Memory Hierarchy 137 Chapter 7. Memory 139  7.1. The memory resource 139  7.2. Characteristics 140  7.3. Memory hierarchy 141  7.4. Memory size and protection 145  7.5. Segmentation 145  7.6. Paging 148  7.7. Memory interleaving and burst mode 151  7.8. Protections, example of the I386 154 Chapter 8. Caches 157  8.1. Cache memory 157  8.2. Replacements algorithms 165 Chapter 9. Virtual Memory 175  9.1. General concept 176  9.2. Rules of the access method 178  9.3 Example of the execution of a program 182  9.4. Example of two-level paging 188  9.5 Paged segmentation 194  9.6. Exercise 197  9.7. Documentation excerpts 198 Part 4. Parallelism and Performance Enhancement 205 Chapter 10. Pipeline Architectures 207  10.1 Motivations and Ideas 207  10.2 Pipeline management problems 212  10.3 Handling branches 218  10.4 Interrupts and exceptions 233 Chapter 11. Example of an Architecture 235  11.1 Presentation 235    11.2. Executing an instruction 240    11.3. Conflict resolution in the DLX 246  11.4. Exercises 252 Chapter 12. Caches in a Multiprocessor Environment 261    12.1. Cache coherence 262  12.2. Examples of snooping protocols 267  12.3. Improvements 275  12.4. Directory-based coherence protocols 275  12.5. Consistency 278  12.6. Exercises 284 Chapter 13. Superscaler Architectures 287  13.1. Superscaler architecture principles 287  13.2. Seeking solutions 290  13.3. Handling the flow of instructions 295  13.4. VLIW architectures 315  13.5. Exercises 321 Part 5. Appendices 325 Appendix A. Hints and Solutions 327  A1.1 The representation of information 327  A1.2. The processor 330  A1.3. Inputs and outputs 331  A1.4. Virtual memory 333  A1.5. Pipeline architectures 335  A1.6. Caches in a multiprocessor environment 341  A1.7. Superscaler architectures 344 Appendix B. Programming Models 347  A2.1. Instruction coding in the I8086 347  A2.2. Instruction set of the DLX architecture 349 Bibliography 351 Index 357

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Gérard Blanchet is the author of Computer Architecture, published by Wiley. Bertrand Dupouy is the author of Computer Architecture, published by Wiley.

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