Asynchronous System-on-Chip Interconnect

Author:   John Bainbridge
Publisher:   Springer London Ltd
Edition:   2002 ed.
ISBN:  

9781852335984


Pages:   139
Publication Date:   28 May 2002
Format:   Hardback
Availability:   Out of stock   Availability explained
The supplier is temporarily out of stock of this item. It will be ordered for you on backorder and shipped when it becomes available.

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Asynchronous System-on-Chip Interconnect


Overview

Asynchronous System-on-Chip Interconnect describes the use of an entirely asynchronous system-bus for the modular construction of integrated circuits. Industry is just awakening to the benefits of asynchronous design in avoiding the problems of clock-skew and multiple clock-domains, an din parallel with this is coming to grips with Intellectual Property (IP) based design flows which emphasise the need for a flexible interconnect strategy. In this book, John Bainbridge investigates the design of an asynchronous on-chip interconnect, looking at all the stages of the design from the choice of wiring layout, through asynchronous signalling protocols to the higher level problems involved in supporting split transactions. The MARBLE bus (the first asynchronous SoC bus) used in a commercial demonstrator chip containing a mixture of asynchronous and synchronous macrocells is used as a concrete example throughout the book.

Full Product Details

Author:   John Bainbridge
Publisher:   Springer London Ltd
Imprint:   Springer London Ltd
Edition:   2002 ed.
Weight:   0.380kg
ISBN:  

9781852335984


ISBN 10:   185233598
Pages:   139
Publication Date:   28 May 2002
Audience:   College/higher education ,  Professional and scholarly ,  Undergraduate ,  Postgraduate, Research & Scholarly
Format:   Hardback
Publisher's Status:   Active
Availability:   Out of stock   Availability explained
The supplier is temporarily out of stock of this item. It will be ordered for you on backorder and shipped when it becomes available.

Table of Contents

1. Introduction.- 2. Asynchronous Design.- 3. System Level Interconnect Principles.- 4. The Physical (Wire) Layer.- 5. The Link Layer.- 6. Protocol Layer.- 7. Transaction Layer.- 8. MARBLE: A Dual-Channel Split Transfer Bus.- 9. Evaluation.- 10. Conclusion.- Appendix A: MARBLE Schematics.- A1 Bus interface top level schematics.- A2 Initiator interface controllers.- A3 Target interface controllers.- A4 Bus drivers and buffers.- A5 Latch controllers.- A6 Centralised bus control units.- References.

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