Architecture-Independent Loop Parallelisation

Author:   Radu C. Calinescu
Publisher:   Springer London Ltd
Edition:   Edition. ed.
ISBN:  

9781852332846


Pages:   190
Publication Date:   14 June 2000
Format:   Hardback
Availability:   Out of stock   Availability explained
The supplier is temporarily out of stock of this item. It will be ordered for you on backorder and shipped when it becomes available.

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Architecture-Independent Loop Parallelisation


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Author:   Radu C. Calinescu
Publisher:   Springer London Ltd
Imprint:   Springer London Ltd
Edition:   Edition. ed.
Dimensions:   Width: 15.20cm , Height: 1.70cm , Length: 24.10cm
Weight:   0.440kg
ISBN:  

9781852332846


ISBN 10:   1852332840
Pages:   190
Publication Date:   14 June 2000
Audience:   College/higher education ,  Professional and scholarly ,  Postgraduate, Research & Scholarly ,  Professional & Vocational
Format:   Hardback
Publisher's Status:   Active
Availability:   Out of stock   Availability explained
The supplier is temporarily out of stock of this item. It will be ordered for you on backorder and shipped when it becomes available.

Table of Contents

INTRODUCTION: Motivation. Parallelisation approach proposed in the book. Organisation of the book.- THE BULK-SYNCHRONOUS PARALLEL MODEL: Introduction. Bulk-synchronous parallel computers. The BSP programming model. The BSP cost model. Assessing the efficiency of BSP code. The development of BSP applications. BSP pseudocode.- DATA DEPENDENCE ANALYSIS AND CODE TRANSFORMATION: Introduction. Data dependence. Code transformation techniques.- COMMUNICATION OVERHEADS IN LOOP NEST SCHEDULING: Introduction. Related work. Communication overheads due to input data. Inter-tile communication overheads. Summary.- TEMPLATE-MATCHING PARALLELISATION: Introduction. Related work. Communication-free scheduling. Wavefront block scheduling. Iterative scheduling. Reduction scheduling. Recurrence scheduling. Scheduling broadcast loop nests. Summary.- GENERIC LOOP NEST PARALLELISATION: Introduction. Related work. Data dependence analysis. Potential parallelism identification. Data and computation partitioning. Communication and synchronisation generation. Performance analysis. Summary.- A STRATEGY AND A TOOL FOR ARCHITECTURE-INDEPENDENT LOOP PARALLELISATION: Introduction. Related work. A two-phase strategy for loop nest parallelisation. BSPscheduler: an architecture-independent loop paralleliser. Summary.- THE EFFECTIVENESS OF ARCHITECTURE-INDEPENDENT LOOP PARALLELISATION: Introduction. Matrix-vector and matrix-matrix multiplication. LU decomposition. Algebraic path problem. Finite difference iteration on a Cartesian grid. Merging. Summary.- CONCLUSIONS: Summary of contributions and concluding remarks. Future work directions.- A: THEOREM PROOFS.- B: SYNTAX OF THE BSPSCHEDULER INPUT LANGUAGE.- C: SYNTAX OF THE BSPSCHEDULER OUTPUT LANGUAGE.- D: AUTOMATICALLY GENERATED CODE FOR EXAMPLE 7.5.- Bibliography.- Index.

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