Overview

A silicon compiler is a software system which can automatically generate an integrated circuit from a user's specification. Anatomy of a Silicon Compiler examines one such compiler in detail, covering the basic framework and design entry, the actual algorithms and libraries which are used, the approach to verification and testing, behavioral synthesis tools and several applications which demonstrate the system's capabilities.

Full Product Details

Author:   Robert W. Brodersen
Publisher:   Springer-Verlag New York Inc.
Imprint:   Springer-Verlag New York Inc.
Edition:   Softcover reprint of the original 1st ed. 1992
Volume:   181
Dimensions:   Width: 15.50cm , Height: 2.00cm , Length: 23.50cm
Weight:   0.587kg
ISBN:  

9781461365860

ISBN 10:   1461365864
Pages:   362
Publication Date:   09 October 2012
Audience:   Professional and scholarly ,  Professional & Vocational
Format:   Paperback
Publisher's Status:   Active
Availability:   Manufactured on demand  
We will order this item for you from a manufactured on demand supplier.

Table of Contents

1 Introduction and History.- 1.1. What is Lager.- 1.2. Users vs. Developers.- 1.3. History.- 1.4. Assembly vs. Behavioral synthesis.- 1.5. Book Organization.- I Framework and Design Entry.- 2 The OCT Data Manager.- 2.1. Basic Structure.- 2.2. Policy Versus Mechanism.- 2.3. The OCT Objects.- 2.4. The OCT Procedural Interface.- 2.5. OCT Physical Policy.- 2.6. OCT Symbolic Policy.- 2.7. Summary.- 3 Lager OCT Policy and the SDL Language.- 3.1. Lager Policies.- 3.2. The Structure_Master View and the SDL Language.- 3.3. The Structure_Instance View.- 3.4. The Physical View.- 3.5. Summary.- 4 Schematic Entry.- 4.1. Schematic Tool Interface.- 4.2. Design Examples.- 4.3. Summary.- 5 Design Management.- 5.1. Parameterization and Library Support.- 5.2. The Design Flow Strategy.- 5.3. Controlling the Design Flow.- 5.4. The Design Management Strategy.- 5.5. Summary.- 6 Design Post-Processing.- 6.1. Capabilities.- 6.2. The Post Processing Tools.- 6.3. Runtime Operation.- 6.4. Summary.- II Silicon Assembly.- 7 Hierarchical Tiling.- 8 Standard Cell Design.- 9 Interactive Floorplanning.- 10 Datapath Generation.- 11 Pad Routing.- III Verification and Testing.- 12 Design Verification.- 13 Behavior and Switch Level Simulation.- 14 Chip and Board Testing.- IV Behavioral Synthesis.- 15 DSP Specification Using the Silage Language.- 16 Synthesis of Datapath Architectures.- 17 From C to Silicon.- 18 An FIR Filter Generator.- V Applications.- 19 The PUMA Processor.- 20 Radon Transform Using the PPPE.- 21 Speech Recognition.- 22 Conclusions and Future Work.- Appendix a Design Example.- A.1. Running Dmoct to Generate a Design.- A.2. Design Post-Processing with Dmpost.- Appendix B Training and Distribution.- B.1. Training.- B.2. Lager Distribution.

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