|
|
|||
|
||||
OverviewInnovative techniques and cutting-edge research in computer arithmetic design Computer arithmetic is a fundamental discipline that drives many modern digital technologies. High-performance VLSI implementations of 3-D graphics, encryption, streaming digital audio and video, and signal processing all require fast and efficient computer arithmetic algorithms. The demand for these fast implementations has led to a wealth of new research in innovative techniques and designs. Advanced Computer Arithmetic Design is the result of ten years of effort at Stanford University under the Sub-Nanosecond Arithmetic Processor (SNAP) project, which author Michael Flynn directs. Written with computer designers and researchers in mind, this volume focuses on design, rather than on other aspects of computer arithmetic such as number systems, representation, or precision. Each chapter begins with a review of conventional design approaches, analyzes the possibilities for improvement, and presents new research that advances the state of the art. The authors present new data in these vital areas: * Addition and the Ling adder * Improvements to floating-point addition * Encoding to reduce execution times for multiplication * The effects of technology scaling on multiplication * Techniques for floating-point division * Approximation techniques for high-level functions such as square root, logarithms, and trigonometric functions * Assessing cost performance of arithmetic units * Clocking to increase computer operation frequency * New implementation of continued fractions to the approximation of functions This volume presents the results of a decade's research in innovative and progressive design techniques. Covering all the most important research topics in the field, Advanced Computer Arithmetic Design is the most up-to-date and comprehensive treatment of new research currently available. Full Product DetailsAuthor: Michael J. Flynn (Computer Architecture and Arithmetic Group, Stanford University, Stanford, CA) , Stuart F. Oberman (Computer Architecture and Arithmetic Group, Stanford University, Stanford, CA)Publisher: John Wiley & Sons Inc Imprint: Wiley-Interscience Dimensions: Width: 16.20cm , Height: 2.10cm , Length: 24.10cm Weight: 0.599kg ISBN: 9780471412090ISBN 10: 0471412090 Pages: 344 Publication Date: 20 April 2001 Audience: College/higher education , Professional and scholarly , Undergraduate , Postgraduate, Research & Scholarly Format: Hardback Publisher's Status: Active Availability: Out of stock ![]() The supplier is temporarily out of stock of this item. It will be ordered for you on backorder and shipped when it becomes available. Table of ContentsPreface. Acknowledgments. Notation. Integer Addition. Floating-Point Addition. Multiplication with Partially Redundant Multiples. Multiplier Topologies. Technology Scaling Effects on Multipliers. Design Issues in Division. Minimizing the Complexity of SRT Tables. Very High-Radix Division. Using a Multiplier for Function Approximation. FUPA. High-Speed Clocking Using Wave Pipelining. Rational Arithmetic. Bibliography. Index.ReviewsDrawing from a decade of research at Stanford Universitys Sub-Nanosecond Arithmetic Processor...[the authors]...explain arithmetic design to computer designers and researchers. (SciTech Book News Vol. 25, No. 2 June 2001) Drawing from a decade of research at Stanford University's Sub-Nanosecond Arithmetic Processor...[the authors]...explain arithmetic design to computer designers and researchers. (SciTech Book News Vol. 25, No. 2 June 2001) Author InformationMICHAEL J. FLYNN is Director of the Sub-Nanosecond Arithmetic Processor (SNAP) project at Stanford University. For the past decade, he has been the leading source of published research in the area of computer arithmetic design. Stuart F. Oberman earned his Phd at Stanford University and is currently manager of VLSI Design at Nishan Systems, San Jose, California. He previously worked at AMD, where he was the architect of the Athlon floating-point unit. His research interests include new algorithms for high-speed computer arithmetic, high-speed switch-fabric design, and architectures for high-throughput network processors. Tab Content 6Author Website:Countries AvailableAll regions |