A Systematic Methodology for Verifying Superscalar Microprocessors

Author:   National Aeronaut Administration (Nasa)
Publisher:   Createspace Independent Publishing Platform
ISBN:  

9781726165341


Pages:   40
Publication Date:   27 August 2018
Format:   Paperback
Availability:   Available To Order   Availability explained
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A Systematic Methodology for Verifying Superscalar Microprocessors


Overview

We present a systematic approach to decompose and incrementally build the proof of correctness of pipelined microprocessors. The central idea is to construct the abstraction function by using completion functions, one per unfinished instruction, each of which specifies the effect (on the observables) of completing the instruction. In addition to avoiding the term size and case explosion problem that limits the pure flushing approach, our method helps localize errors, and also handles stages with interactive loops. The technique is illustrated on pipelined and superscalar pipelined implementations of a subset of the DLX architecture. It has also been applied to a processor with out-of-order execution.Srivas, Mandayam and Hosabettu, Ravi and Gopalakrishnan, GaneshLangley Research CenterMICROPROCESSORS; COMPUTER SYSTEMS DESIGN; PIPELINING (COMPUTERS); ARCHITECTURE (COMPUTERS); MULTIPROCESSING (COMPUTERS); DATA PROCESSING EQUIPMENT; COMPUTER SYSTEMS PERFORMANCE; REGISTERS (COMPUTERS); THEOREM PROVING...

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Author:   National Aeronaut Administration (Nasa)
Publisher:   Createspace Independent Publishing Platform
Imprint:   Createspace Independent Publishing Platform
Dimensions:   Width: 21.60cm , Height: 0.20cm , Length: 27.90cm
Weight:   0.118kg
ISBN:  

9781726165341


ISBN 10:   1726165345
Pages:   40
Publication Date:   27 August 2018
Audience:   General/trade ,  General
Format:   Paperback
Publisher's Status:   Active
Availability:   Available To Order   Availability explained
We have confirmation that this item is in stock with the supplier. It will be ordered in for you and dispatched immediately.

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