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OverviewThis work is building on results from the book named “A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness” by M. Kovalev, S.M. Müller, and W.J. Paul, published as LNCS 9000 in 2014. It presents, at the gate level, construction and correctness proof of a multi-core machine with pipelined processors and extensive operating system support with the following features: • MIPS instruction set architecture (ISA) for application and for system programming • cache coherent memory system • store buffers in front of the data caches • interrupts and exceptions • memory management units (MMUs) • pipelined processors: the classical five-stage pipeline is extended by two pipeline stages for address translation • local interrupt controller (ICs) supporting inter-processor interrupts (IPIs) • I/O-interrupt controller and a disk Full Product DetailsAuthor: Petro Lutsyk , Jonas Oberhauser , Wolfgang J. PaulPublisher: Springer Nature Switzerland AG Imprint: Springer Nature Switzerland AG Edition: 1st ed. 2020 Volume: 9999 Weight: 0.973kg ISBN: 9783030432423ISBN 10: 3030432424 Pages: 628 Publication Date: 10 May 2020 Audience: Professional and scholarly , Professional & Vocational Format: Paperback Publisher's Status: Active Availability: Manufactured on demand  We will order this item for you from a manufactured on demand supplier. Table of ContentsReviewsAuthor InformationTab Content 6Author Website:Countries AvailableAll regions |
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