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This dissertation, A New Optimization Model for VLSI Placement by 高雲龍, Wan-lung, Ko, was obtained from The University of Hong Kong (Pokfulam, Hong Kong) and is being sold pursuant to Creative Commons: Attribution 3.0 Hong Kong License. The content of this dissertation has not been altered in any way. We have altered the formatting in order to facilitate the ease of printing and reading of the dissertation. All rights not granted by the above license are retained by the author. Abstract: Abstract of thesis entitled A New Optimization Model for VLSI Placement submitted by Robin Ko Wan Lung for the degree of Master of Philosophy at the University of Hong Kong in May, 1998. For years, the estimated net length parameter has been the dominating model used in cost functions for the VLSI placement and routing problem. The intention there is to reduce the final circuit layout area through a sequence of placement steps. Since the net length model is not difficult to compute and intuitively speaking, should generate a fairly good solution, few research has been conducted in the search for a new model which may have a closer tie with the layout optimization objective. This research presents a new model which can be used to formulate cost functions for various VLSI placement problems. A formal proof indicating the close relationship of the parameter, namely crossing, with the conventional channel density is given. Such proof, which has never been established in the net length model, looks promising as the chance of reducing channel density can be increased. Apart from the above breakthrough, the new model have several advantages. Theoretically, it has a lower bound of zero, i.e. no nets will make crosses with another. In addition, the crossing notion of a standard cell is inherently a two- dimensional model and its computation is localised to those cells connected it. Crossing model is intended to be applied on parallel optimization algorithm in future. The above advantages of our model will be illustrated by a post-optimization step after standard cell placement. At the same time, a heuristic algorithm with the complexity of the algorithm of Ο(nn )+Ο is also proposed using the crossing ( ) mn model. Experiment using our model with the proposed algorithm have been applied on several benchmarks. A reduction of up to 4% of the layout area was achieved. Though the reduction seems not to be very significant at present stage, this algorithm is essentially very fast. Moreover, one thing should be noted is that the reconnection will not change the relative location of the standard cells. Experimental results also indicate that when our model is applied on global routing phase together with our post-optimization step, futher reduction could be obtained. DOI: 10.5353/th_b2981293 Subjects: Integrated circuits - Very large scale integration - Design and construction

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